The present invention relates generally to integrated circuit (IC) design, and more particularly to multiplexer methods and apparatus.
Multiplexers are widely used to multiplex signals. For example, microprocessors and digital signal processors may include one or more multiplexers. For lower power applications, static multiplexers are preferred. Although static multiplexers can be built using CMOS gates, a transmission-gate, pass-gate or tristate transistor topology is generally used to create multiplexers that receive a larger number of input signals and provide a better overall performance (e.g., are faster).
FIG. 1 is an exemplary single-level multiplexer system 100 for multiplexing signals. The multiplexer system 100 includes a decoder 102 coupled to a multiplexer 104. Using standard decoding methods, the decoder 102 may receive an n-bit signal via a bus 106, for example, and output 2n select signals. The select signals are input to the multiplexer 104, along with a plurality of data signals (B0-B2nxe2x88x921).
In a hot select embodiment, the number of select signals may correspond to the number of data signals input to the multiplexer 104; and the select signals output by the decoder 102 include only one signal (or bit) that is of a high logic state. The remaining select signals (or bits) are of a low logic state. Based on the select signals input to the multiplexer 104, the multiplexer 104 outputs one of the data signals B0-B2nxe2x88x921 input to the multiplexer 104 at an output 108 of the multiplexer. For example, if a two-bit signal is input to the decoder 102, the decoder 102 outputs a 4-bit select signal. The bits of the 4-bit signal are input to the multiplexer 104 as four select signals that allow the multiplexer 104 to select between four data input signals B0-B3. If select signals of xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d are input to the multiplexer 104, the multiplexer 104 outputs the input signal B0 at the output 108. If select signals of 0100 are input to the multiplexer 104, the multiplexer 104 outputs the input signal B1 at the output 108. The signals B2 and B3 may be similarly output via the multiplexer 104. In the first example, the multiplexer 104 creates a logic delay in the path of data signal B0. Likewise, in the second example, the multiplexer 104 creates a logic delay in the path of data signal B1. The logic delay created by a multiplexer 104 is equivalent to the delay created by two logic gate operations.
Although in the above example the multiplexer 104 receives four select signal inputs and four data signal inputs, the multiplexer 104 may be configured to receive a smaller or greater number of select signals and data signals. However, the performance of a single-level multiplexer system degrades as the number of data signals input to a multiplexer is increased. More specifically, due to capacitance effects resulting from the increased number of data signals input to the multiplexer, the switching properties of the multiplexer are affected and overall performance of the multiplexer is degraded.
To avoid the performance degradation associated with the single-level multiplexer system 100 shown in FIG. 1, a multi-level multiplexer system may be used to multiplex a large number of signals. FIG. 2 is an exemplary multi-level multiplexer system 200 for multiplexing signals. The multi-level multiplexer system 200 includes a first decoder circuit 202 coupled to a plurality of multiplexers 204-210. Similar to the decoder 102 of FIG. 1, the first decoder circuit 202 may receive an m-bit signal via a bus 212, for example, and output 2m select signals using standard decoding methods. The 2m select signals are input to each of the multiplexers 204-210, along with a plurality of data signals (e.g., an equal number of data signals at each multiplexer 204-210). The number of select signals may correspond to the number of data signals input to each of the multiplexers 204-210.
Similar to the select signals output by the decoder 102 of FIG. 1, the select signals output by the first decoder circuit 202 of FIG. 2 may include only one signal (or bit) that is a high logic state. The remaining select signals (or bits) are of a low logic state. Based on the select signals input to the multiplexers 204-210, each multiplexer 204-210 outputs one of the plurality of data signals input to that multiplexer. Each multiplexer 204-210 simultaneously selects one input signal to output from the plurality of data signals input to that multiplexer, and outputs the selected signal to a second level multiplexer 212.
As an example, if a two-bit signal is input to the first decoder circuit 202, the first decoder circuit 202 outputs a four-bit signal. The bits of the four-bit signal are input to each of the multiplexers 204-210 as four select signals. Assuming the multiplexers 204-210 receive data signals A0-A3, B0-B3, C0-C3 and D0-D3, respectively, as inputs, select signals of xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d input to each of the multiplexers 204-210 causes the multiplexer 204-210 to output data signals A0, B0, C0, and D0, respectively, to the second level multiplexer 212.
The multi-level multiplexer system 200 includes a second decoder circuit 214 coupled to the second level multiplexer 212. The second decoder circuit 214 may receive an input from an (nxe2x88x92m)-bit signal via a bus 216, for example, and output 2(nxe2x88x92m) select signals where the multi-level multiplexer system 200 provides 2n to 1 multiplexing. The 2(nxe2x88x92m) signals are input to the second level multiplexer 212 as select signals and the signals (e.g., Ao, Bo, Co, Do) output from each multiplexer 204-210 in the first-level of the multi-level multiplexer system are input to the second level multiplexer 212 as data signals.
Based on the 2(nxe2x88x92m) signals input to the second level multiplexer 212, the multiplexer 212 outputs one of the data signals (e.g., Ao, Bo, Co, Do) input to the multiplexer 216. For example, if m=2 and n=4, the first and second level of the multi-level multiplexer system to 200 will each provide 4-to-1 multiplexing. The overall system 200 will therefore provide 16-to-1 multiplexing. More specifically, at a first level the system 200 of FIG. 2 provides multiplexing of 16 signals into one signal by first multiplexing each of a plurality of small groups of data signals (A0-A2mxe2x88x921, B0-B2mxe2x88x921, C0-C2mxe2x88x921, D0-D2mxe2x88x921) in parallel to select one data signal from each of those groups (e.g., Ao, Bo, Co, Do). These selected signals are input to the second level multiplexer 212. The multiplexer 212 in the second level selects one signal (e.g., Ao, Bo, Co, Do) from the first level selected signals to output (via an output 220) based on the select signals provided via the second decoder 214.
Although the multi-level multiplexer system 200 provides better performance when a larger number of data signals is to be multiplexed, the system 200 introduces a logic delay in the path of a data signal at both the first and second level of multiplexing. Because the multi-level multiplexer system 200 creates two multiplexer logic delays, the performance (e.g., speed) of the system 200 may not be suitable for many applications. Therefore, methods and apparatus for improved multiplexer systems are desired.
In a first aspect of the invention, a method is provided for selecting a signal from a plurality of signals. The method includes the steps of (1) providing a plurality of multiplexers, each multiplexer adapted to selectively output one of a plurality of signals input by the multiplexer using an output of the multiplexer; (2) selecting an input signal from one of the plurality of multiplexers to output; (3) outputting the selected input signal from the output of the one of the plurality of multiplexers; (4) forcing the outputs of the other of the plurality of multiplexers to a predetermined logic state; and (5) combining the outputs of the plurality of multiplexers so as to output the selected input signal.
In a second aspect of the invention, a multiplexer circuit is provided that is adapted to select a signal from a plurality of signals. The multiplexer circuit comprises a plurality of multiplexers, each multiplexer adapted to selectively output one of a plurality of signals input by the multiplexer using an output of the multiplexer. The multiplexer circuit also includes (1) a first decoder circuit coupled to the plurality of multiplexers and adapted to generate a plurality of select signals to select an input signal from one of the plurality of multiplexers to output; and (2) a second decoder circuit coupled to the plurality of multiplexers and adapted to generate a plurality of activation signals to force the outputs of the other of the plurality of multiplexers to a predetermined logic state. The multiplexer circuit further includes a logic circuit coupled to the plurality of multiplexers and adapted to combine the outputs of the plurality of multiplexers so as to output the selected input signal. Numerous other aspects are provided.
Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.